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Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
DESCRIPTION
The M5M29KB/T331AVP are 3.3V-only high speed 33,554,432-bit CMOS boot block FLASH Memories with alternating BGO(Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for mobile and personal computing, and communication products. M5M29KB/T331AVP provides for Software Lock Release function. Usually, all memory blocks are locked and can not be programmed or erased, when WP# is low. Using Software Lock Release function, program or erase operation can be executed.
FEATURES
Access time Random Page 70ns (Max.) 25ns(Max.) VCC= 3.0 ~ 3.6V
The M5M29KB/T331AVP are fabricated by CMOS technology Supply voltage Ta=-40 ~ 85 C for the peripheral circuit and DINOR IV(Divided bit-line NOR IV) Ambient temperature architecture for the memory cell, and are available in 48pin Package 48pin TSOP(Type-I), Lead pitch 0.5mm TSOP(I) for lead free use. Outer-lead finishing : Sn-Cu
APPLICATION
Digital Cellar Phone, Telecommunication, PDA, Car Navigation System, Video Game Machine
PIN CONFIGURATION (TOP VIEW)
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RP# NC WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
M5M29KB/T331AVP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 BYTE# GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0
12.0 mm
20.0 mm
VCC GND A0-A21 DQ0-DQ15 CE# OE# : VCC : GND : Address : Data I/O : Chip enable : Output enable WE# WP# RP# BYTE# RY/BY# NC : Write enable : Write protect : Reset power down : Byte enable : Ready/Busy : Non Connection
Outline 48P3R-C
1
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
32M Flash Memory Block Diagram
Vcc
GND
A0 to A20 CE# OE# WE# WP# RP# BYTE#
32Mbit DINOR IV Flash Memory
RY/BY#
DQ0 to DQ15
Capacitance
Symbol CIN Parameter Conditions Ta=25C, f=1MHz, Vin=Vout=0V Min. Limits Typ. Max. 12 12 Unit pF pF
Input A20-A0, OE#, WE#, CE#, WP#, capacitance RP#,BYTE# Output COUT DQ15-DQ0,RY/BY# Capacitance
2
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Flash Memory Part
Description
The 32M-bit DINOR IV(Divided bit line NOR IV) Flash Memory is 3.3V-only high speed 33,554,432-bit CMOS boot block Flash Memory. Alternating BGO(Back Ground Operation) feature of the device allows Program or Erase operations to be performed in one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for communication products and cellular phone.The Flash Memory is fabricated by CMOS technology for the peripheral circuits and DINOR IV architecture for the memory cells. - Auto Erase Erase time Erase unit Bank(I) Boot Block Main Block Bank(II) Bank(III) Bank(IV) - Boot Block Main Block Main Block Main Block 4K-word x2/ 8K-byte x2 32K-word x7 / 64K-byte x7 32K-word x8 / 64K-byte x8 32K-word x24 / 64K-byte x24 32K-word x24 / 64K-byte x24 100Kcycles Parameter Block 4K-word x6 / 8K-byte x6 Main Block 150ms/block (typ.)
- Program/Erase cycles Bottom Boot 2,097,152-word x 16-bit 4,194,304-byte x 8-bit - Supply Voltage - Access time Random Access Random Page Read - Read - Page Read (After Automatic Power Down) - Program/Erase Standby Deep Power Down mode Program Time Word Program Byte Program Page Program Program Unit Word/Byte Program Page Program 1word/ 1Byte 128 words/ 256 bytes 30s/word(typ.) 30s/byte(typ.) 4ms(typ.) 70ns(Max.) 25ns(Max.) 108mW (Max. at 5MHz) 36mW (Max.) 0.33W(typ.) 126mW(Max.) 0. 33W(typ.) 0. 33W(typ.) VCC = 3.0 ~ 3.6V Top Boot M***B33****** M***T33******
Features
-Organization
- The Other Functions Software Command Control Software Lock Release(while WP# is low) Erase Suspend/Resume Program Suspend/Resume Status Register Read Alternating Back Ground Program/Erase Operation Between Bank(I), Bank(II), Bank(III) and Bank(IV) Random Page Read
- Auto Program for Bank(I) - Bank(IV)
3
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Block Diagram (32Mbit Flash Memory)
128word Page Buffer
A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
X-Decoder
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
Main Block 70 32Kword
Bank(IV) 24blocks
* * * * * * * * * * *
Main Block 47 32Kword Main Block 46 32Kword
VCC GND
Bank(III) 24blocks
Address A10 Input A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
* * * * * * * * * * *
Main Block 23 32Kword Main Block 22 32Kword
Bank(II) 8blocks
* * *
Main Block 15 32Kword Main Block 14 32Kword
*
Bank(I) 15blocks Main Block 8 32Kword Parameter Block 7 4Kword
*
Parameter Block 2 4Kword Boot Block 1 4Kword Boot Block 0 4Kword
Y-Decoder
* * * * *
Y-Gate / Sense Amp.
*************************** Status / ID Register
Multiplexer
Chip Enable
CE#
Output Enable OE#
***************************
Command User Interface
Write Enable WE# Write WP# Protect Reset RP# /PowerDown BYTE
READY/BUSY
BYTE#
Write State Machine
I/O Buffer
***************************
RY/ BY#
***************************
DQ15 / A-1
DQ14
Data I/O
DQ1 DQ0
4
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Function of Flash Memory
The 32M-bit DINOR IV Flash Memory includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and word/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. A Deep Power Down mode is enabled when the RP# pin is at GND, minimizing power consumption.
Output Disable
When OE# is at VIH, output from the devices is disabled. Data input/output are in a high-impedance (High-Z) state.
Standby
When CE# is at VIH, the device is in the standby mode and its power consumption is reduced. Data input/output are in a high-impedance (High-Z) state. If the memory is deselected during block erase or program, the internal control circuits remain active and the device consumes normal active power until the operation completes.
Deep Power Down Read
The 32M-bit DINOR IV Flash Memory has four read modes, which accesses to the memory array, the Page Read, the Device Identifier and the Status Register. The appropriate read commands are required to be written to the CUI. Upon initial device power up or after exit from deep power down, the 32M-bit DINOR IV Flash Memory automatically resets to read array mode. In the read array mode and in the conditions are low level input to OE#, high level input to WE# and RP#, low level input to CE# and address signals to the address inputs (A20 - A0: Word mode / A20-A-1: Byte mode) the data of the addressed location to the data input/output (DQ15-DQ0: Word mode / DQ7- DQ0: Byte mode) is output. When RP# is at VIL, the device is in the deep power down mode and its power consumption is substantially low. During read modes, the memory is deselected and the data input/output are in a high-impedance (High-Z) state. After return from power down, the CUI is reset to Read Array, and the Status Register is cleared to value 80H. During block erase or program modes, RP# low will abort either operation. Memory array data of the block being altered become invalid.
Automatic Power Down (Auto-PD)
The Automatic Power Down minimizes the power consumption during read mode. The device automatically turns to this mode when any addresses or CE# isn't changed more than 200ns after the last alternation. The power consumption becomes the same as the stand-by mode. During this mode, the output data is latched and can be read out. New data is read out correctly when addresses are changed.
Write
Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register. They also enable block erase and program. The CUI is written by bringing WE# to low level and OE# is at high level, while CE# is at low level. Address and data are latched on the earlier rising edge of WE# and CE#. Standard micro processor write timings are used.
BBR(Back Bank array Read)
In the 32M-bit DINOR IV Flash Memory , when one memory address is read according to a Read Mode in the case of the same as an access when a Read Mode command is input, an another Bank memory data can be read out (Random or Page Mode) by changing an another Bank address.
Alternating Background Operation (BGO)
The 32M-bit DINOR IV Flash Memory allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. Array Read operation with the other bank in BGO is performed by changing the bank address without any additional command. When the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. The access time with BGO is the same as the normal read operation. BGO must be between Bank(I), Bank(II), Bank(III) and Bank(IV).
5
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Software Command Definitions
The device operations are selected by writing specific software command into the Command User Interface.
Clear Status Register Command (50H)
The Erase Status, Program Status and Block Status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command of 50H. These bits indicate various failure conditions.
Read Array Command (FFH)
The device is in Read Array mode on initial device power up and after exit from deep power down, or by writing FFH to the Command User Interface. After starting the internal operation the device is set to the read status register mode automatically.
Block Erase / Confirm Command (20H/D0H)
Automated block erase is initiated by writing the Block Erase command of 20H followed by the Confirm command of D0H. An address within the block to be erased is required. The WSM executes iterative erase pulse application and erase verify operation.
Read Device Identifier Command (90H)
We can normally read device identifier codes when Read Device Identifier Code Command (90H) is written to the command latch. Following the command write, the manufacturer code and the device code can be read from A0 address 0H and 1H in a bank address, respectively.
Read Status Register Command (70H)
The Status Register is read after writing the Read Status Register command of 70H to the Command User Interface. Also, after starting the internal operation the device is set to the Read Status Register mode automatically. The contents of Status Register are latched on the later falling edge of OE# or CE#. When status read is required, OE# or CE# must be toggled every status read.
Program Commands A) Word / Byte Program (40H)
Word / Byte program is executed by a two-command sequence. The Word/Byte program Setup command of 40H is written to the Command Interface, followed by a second write specifying the address and data to be written. The WSM controls the program pulse application and verify operation.
B) Page Program for Data Blocks (41H)
Page Program allows fast programming of 128 words/ 256 bytes of data. Writing of 41H initiates the page program operation for the Data area. From 2nd cycle to 129th cycle(Word mode)/ 257th cycle(Byte mode), write data must be serially inputted. Address A6-A0(Word mode)/ A6-A-1(Byte mode) have to be incremented from 00H to 7FH. After completion of data loading, the WSM controls the program pulse application and verify operation.
Page Read Command (F3H)
The Page Read command (F3H) timing can be used by writing the first command and CE# falls VIL or changing the address(A20-A2) is necessary to start activating page read mode. This command is fast random 4 words read. During the read cycle operation it is necessary to fix CE# low and change addresses which are defined by A0 and A1(or A-1 to A1) at random continuously. The mode is kept until RP# is set to VIL or this chip is powered down. The first read of Page Read timing is the same as normal read (ta(CE)). CE# should be fallen VIL. The read timing after the first is fast read (ta(PAD)). In the page read mode the upper address(A20-A2) is supposed not to be clocked during read operation. Otherwise the access time is as same as normal read.
C) Single Data Load to Page Buffer (74H) / Page Buffer to Flash (0EH/D0H)
Single data load to the page buffer is performed by writing 74H followed by a second write specifying the column address and data. Distinct data up to 128word can be loaded to the page buffer by this two-command sequence. On the other hand, all of the loaded data to the page buffer is programmed simultaneously by writing Page Buffer to Flash command of 0EH followed by the confirm command of D0H. After completion of programming the data on the page buffer is cleared automatically.
6
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Flash to Page Buffer Command (F1H/D0H)
Array data load to the page buffer is performed by writing the Flash to Page Buffer command of F1H followed by the Confirm command of D0H. An address within the page to be loaded is required. Then the array data can be copied into the other pages within the same bank by using the Page Buffer to Flash command.
Power Supply Voltage
When the power supply voltage is less than VLKO, Low VCC Lock-Out voltage, the device is set to the Read-only mode. A delay time of 2s is required before any device operation is initiated. The delay time is measured from the time Flash VCC reaches Flash VCCmin (3.0V). During power up, RP# = GND is recommended. Falling in Busy status is not recommended for possibility of damaging the device.
Clear Page Buffer Command (55H/D0H)
Loaded data to the page buffer is cleared by writing the Clear Page Buffer command of 55H followed by the Confirm command of D0H. This command is valid for clearing data loaded by Single Data Load to Page Buffer command.
Memory Organization
The 32M-bit DINOR IV Flash Memory is constructed by 2 boot blocks of 4K words/ 8K bytes, 6 parameter blocks of 4K words/ 8K bytes and 7 main blocks of 32K words/ 64K bytes in Bank(I), by 8 main blocks of 32K words/ 64K bytes in Bank(II) and by 24 main blocks of 32K words/ 64K bytes in Bank(III) and Bank(IV).
Data Protection
The 32M-bit DINOR IV Flash Memory has a master Write Protect pin (WP#). When WP# is at VIH, all blocks can be programmed or erased. When WP# is low, all blocks are in locked mode which prevents any modifications to memory blocks. Software Lock Release function is only command which allows to program or erase.
Suspend/Resume Command (B0H/D0H)
Writing the Suspend command of B0H during block erase operation interrupts the block erase operation and allows read out from another block of memory. Writing the Suspend command of B0H during program operation interrupts the program operation and allows read out from another block of memory. The Bank address is required when writing the Suspend/Resume Command. The device continues to output Status Register data when read, after the Suspend command is written to it. Polling the WSM Status and Suspend Status bits will determine when the erase operation or program operation has been suspended. At this point, writing of the Read Array command to the CUI enables reading data from blocks other than that which is suspended. When the Resume command of D0H is written to the CUI, the WSM will continue with the erase or program processes.
Erase All Unlocked Blocks Command (A7H/D0H)
The command sequence enable us to erase all blocks. The command can be used by writing Setup command A7H(1st cycle) and confirm command D0H(2nd cycle). The sequence is not valid in case of WP#=VIL.
7
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Block Organization
x8 (Byte Mode) 1B0000H1BFFFFH 1A0000H1AFFFFH 190000H19FFFFH 180000H18FFFFH 170000H17FFFFH 160000H16FFFFH 150000H15FFFFH 140000H14FFFFH 130000H13FFFFH 120000H12FFFFH 110000H11FFFFH 100000H10FFFFH F0000HFFFFFH E0000HEFFFFH D0000HDFFFFH C0000HCFFFFH B0000HBFFFFH A0000HAFFFFH 90000H9FFFFH 80000H8FFFFH 70000H7FFFFH 60000H6FFFFH 50000H5FFFFH 40000H4FFFFH 30000H3FFFFH 20000H2FFFFH 10000H1FFFFH 0E000H0FFFFH 0C000H0DFFFH 0A000H0BFFFH 08000H09FFFH 06000H07FFFH 04000H05FFFH 02000H03FFFH 00000H01FFFH A20-A-1 (Byte Mode) x16 (Word Mode) D8000HDFFFFH D0000HD7FFFH C8000HCFFFFH C0000HC7FFFH B8000HBFFFFH B0000HB7FFFH A8000HAFFFFH A0000HA7FFFH 98000H9FFFFH 90000H97FFFH 88000H8FFFFH 80000H87FFFH 78000H7FFFFH 70000H77FFFH 68000H6FFFFH 60000H67FFFH 58000H5FFFFH 50000H57FFFH 48000H4FFFFH 40000H47FFFH 38000H3FFFFH 30000H37FFFH 28000H2FFFFH 20000H27FFFH 18000H1FFFFH 10000H17FFFH 08000H0FFFFH 07000H07FFFH 06000H06FFFH 05000H05FFFH 04000H04FFFH 03000H03FFFH 02000H02FFFH 01000H01FFFH 00000H00FFFH A20-A0 (Word Mode)
32M-bit DINOR(IV) Flash Memory Map (Bottom Boot)
x8 (Byte Mode) 3F0000H3FFFFFH 3E0000H3EFFFFH 3D0000H3DFFFFH 3C0000H3CFFFFH 3B0000H3BFFFFH x16 (Word Mode) 1F8000H1FFFFFH 1F0000H1F7FFFH 1E8000H1EFFFFH 1E0000H1E7FFFH 1D8000H1DFFFFH 1D0000H1D7FFFH 1C8000H1CFFFFH 1C0000H1C7FFFH 1B8000H1BFFFFH 1B0000H1B7FFFH 1A8000H1AFFFFH 1A0000H1A7FFFH 198000H19FFFFH 190000H197FFFH 188000H18FFFFH 180000H187FFFH 178000H17FFFFH 170000H177FFFH 168000H16FFFFH 160000H167FFFH 158000H15FFFFH 150000H157FFFH 148000H14FFFFH 140000H147FFFH 138000H13FFFFH 130000H137FFFH 128000H12FFFFH 120000H127FFFH 118000H11FFFFH 110000H117FFFH 108000H10FFFFH 100000H107FFFH F8000HFFFFFH F0000HF7FFFH E8000HEFFFFH E0000HE7FFFH A20-A0 (Word Mode)
32Kw ord MAIN BLOCK 34 32Kw ord MAIN BLOCK 33 32Kw ord MAIN BLOCK 32 32Kw ord MAIN BLOCK 31 32Kw ord MAIN BLOCK 30
32Kw ord MAIN BLOCK 70 32Kw ord MAIN BLOCK 69 32Kw ord MAIN BLOCK 68 32Kw ord MAIN BLOCK 67 32Kw ord MAIN BLOCK 66 32Kw ord MAIN BLOCK 65 32Kw ord MAIN BLOCK 64 32Kw ord MAIN BLOCK 63 32Kw ord MAIN BLOCK 62 32Kw ord MAIN BLOCK 61 32Kw ord MAIN BLOCK 60 32Kw ord MAIN BLOCK 59 32Kw ord MAIN BLOCK 58 32Kw ord MAIN BLOCK 57 32Kw ord MAIN BLOCK 56
BANK(III) BANK(II) BANK(I)
32Kw ord MAIN BLOCK 29 32Kw ord MAIN BLOCK 28 32Kw ord MAIN BLOCK 27 32Kw ord MAIN BLOCK 26 32Kw ord MAIN BLOCK 25 32Kw ord MAIN BLOCK 24 32Kw ord MAIN BLOCK 23 32Kw ord MAIN BLOCK 22 32Kw ord MAIN BLOCK 21 32Kw ord MAIN BLOCK 20 32Kw ord MAIN BLOCK 19 32Kw ord MAIN BLOCK 18 32Kw ord MAIN BLOCK 17 32Kw ord MAIN BLOCK 16 32Kw ord MAIN BLOCK 15 32Kw ord MAIN BLOCK 14 32Kw ord MAIN BLOCK 13 32Kw ord MAIN BLOCK 12 32Kw ord MAIN BLOCK 11 32Kw ord MAIN BLOCK 10 32Kw ord MAIN BLOCK 9 32Kw ord MAIN BLOCK 8
4Kword PARAMETER BLOCK 7 4Kword PARAMETER BLOCK 6 4Kword PARAMETER BLOCK 5 4Kword PARAMETER BLOCK 4 4Kword PARAMETER BLOCK 3 4Kword PARAMETER BLOCK 2
3A0000H3AFFFFH 390000H39FFFFH 380000H38FFFFH 370000H37FFFFH 360000H36FFFFH 350000H35FFFFH 340000H34FFFFH 330000H33FFFFH 320000H32FFFFH 310000H31FFFFH 300000H30FFFFH 2F0000H2FFFFFH 2E0000H2EFFFFH 2D0000H2DFFFFH 2C0000H2CFFFFH 2B0000H2BFFFFH 2A0000H2AFFFFH 290000H29FFFFH 280000H28FFFFH 270000H27FFFFH 260000H26FFFFH 250000H25FFFFH 240000H24FFFFH 230000H23FFFFH 220000H22FFFFH 210000H21FFFFH 200000H20FFFFH 1F0000H1FFFFFH 1E0000H1EFFFFH 1D0000H1DFFFFH 1C0000H1CFFFFH A20-A-1 (Byte Mode)
BANK(IV) BANK(III)
32Kw ord MAIN BLOCK 55 32Kw ord MAIN BLOCK 54 32Kw ord MAIN BLOCK 53 32Kw ord MAIN BLOCK 52 32Kw ord MAIN BLOCK 51 32Kw ord MAIN BLOCK 50 32Kw ord MAIN BLOCK 49 32Kw ord MAIN BLOCK 48 32Kw ord MAIN BLOCK 47 32Kw ord MAIN BLOCK 46 32Kw ord MAIN BLOCK 45 32Kw ord MAIN BLOCK 44 32Kw ord MAIN BLOCK 43 32Kw ord MAIN BLOCK 42 32Kw ord MAIN BLOCK 41 32Kw ord MAIN BLOCK 40 32Kw ord MAIN BLOCK 39 32Kw ord MAIN BLOCK 38 32Kw ord MAIN BLOCK 37 32Kw ord MAIN BLOCK 36 32Kw ord MAIN BLOCK 35
4Kw ord BOOT BLOCK 1 4Kw ord BOOT BLOCK 0
8
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Block Organization
x8 (Byte Mode) 230000H23FFFFH 220000H22FFFFH 210000H21FFFFH 200000H20FFFFH 1F0000H1FFFFFH 1E0000H1EFFFFH 1D0000H1DFFFFH 1C0000H1CFFFFH 1B0000H1BFFFFH 1A0000H1AFFFFH 190000H19FFFFH 180000H18FFFFH 170000H17FFFFH 160000H16FFFFH 150000H15FFFFH 140000H14FFFFH 130000H13FFFFH 120000H12FFFFH 110000H11FFFFH 100000H10FFFFH F0000HFFFFFH E0000HEFFFFH D0000HDFFFFH C0000HCFFFFH B0000HBFFFFH A0000HAFFFFH 90000H9FFFFH 80000H8FFFFH 70000H7FFFFH 60000H6FFFFH 50000H5FFFFH 40000H4FFFFH 30000H3FFFFH 20000H2FFFFH 10000H1FFFFH 00000H0FFFFH A20-A-1 (Byte Mode) x16 (Word Mode) 118000H11FFFFH 110000H117FFFH 108000H10FFFFH 100000H107FFFH F8000HFFFFFH F0000HF7FFFH E8000HEFFFFH E0000HE7FFFH D8000HDFFFFH D0000HD7FFFH C8000HCFFFFH C0000HC7FFFH B8000HBFFFFH B0000HB7FFFH A8000HAFFFFH A0000HA7FFFH 98000H9FFFFH 90000H97FFFH 88000H8FFFFH 80000H87FFFH 78000H7FFFFH 70000H77FFFH 68000H6FFFFH 60000H67FFFH 58000H5FFFFH 50000H57FFFH 48000H4FFFFH 40000H47FFFH 38000H3FFFFH 30000H37FFFH 28000H2FFFFH 20000H27FFFH 18000H1FFFFH 10000H17FFFH 08000H0FFFFH 00000H07FFFH A20-A0 (Word Mode)
32M-bit DINOR(IV) Flash Memory Map (Top Boot)
x8 (Byte Mode) 3FE000H3FFFFFH 3FC000H3FDFFFH 3FA000H3FBFFFH 3F8000H3F9FFFH 3F6000H3F7FFFH 3F4000H3F5FFFH 3F2000H3F3FFFH 3F0000H3F1FFFH 3E0000H3EFFFFH 3D0000H3DFFFFH 3C0000H3CFFFFH 3B0000H3BFFFFH 3A0000H3AFFFFH 390000H39FFFFH 380000H38FFFFH 370000H37FFFFH 360000H36FFFFH 350000H35FFFFH 340000H34FFFFH 330000H33FFFFH 320000H32FFFFH 310000H31FFFFH 300000H30FFFFH 2F0000H2FFFFFH 2E0000H2EFFFFH 2D0000H2DFFFFH 2C0000H2CFFFFH 2B0000H2BFFFFH 2A0000H2AFFFFH 290000H29FFFFH 280000H28FFFFH 270000H27FFFFH 260000H26FFFFH 250000H25FFFFH 240000H24FFFFH A20-A-1 (Byte Mode) x16 (Word Mode) 1FF000H1FFFFFH 1FE000H1FEFFFH 1FD000H1FDFFFH 1FC000H1FCFFFH 1FB000H1FBFFFH 1FA000H1FAFFFH 1F9000H1F9FFFH 1F8000H1F8FFFH 1F0000H1F7FFFH 1E8000H1EFFFFH 1E0000H1E7FFFH 1D8000H1DFFFFH 1D0000H1D7FFFH 1C8000H1CFFFFH 1C0000H1C7FFFH 1B8000H1BFFFFH 1B0000H1B7FFFH 1A8000H1AFFFFH 1A0000H1A7FFFH 198000H19FFFFH 190000H197FFFH 188000H18FFFFH 180000H187FFFH 178000H17FFFFH 170000H177FFFH 168000H16FFFFH 160000H167FFFH 158000H15FFFFH 150000H157FFFH 148000H14FFFFH 140000H147FFFH 138000H13FFFFH 130000H137FFFH 128000H12FFFFH 120000H127FFFH A20-A0 (Word Mode)
32Kw ord MAIN BLOCK 35 32Kw ord MAIN BLOCK 34 32Kw ord MAIN BLOCK 33 32Kw ord MAIN BLOCK 32
4Kw ord BOOT BLOCK 70 4Kw ord BOOT BLOCK 69
4Kword PARAMETER BLOCK 68 4Kword PARAMETER BLOCK 67 4Kword PARAMETER BLOCK 66 4Kword PARAMETER BLOCK 65 4Kword PARAMETER BLOCK 64
BANK(III) BANK(IV)
32Kw ord MAIN BLOCK 31 32Kw ord MAIN BLOCK 30 32Kw ord MAIN BLOCK 29 32Kw ord MAIN BLOCK 28 32Kw ord MAIN BLOCK 27 32Kw ord MAIN BLOCK 26 32Kw ord MAIN BLOCK 25 32Kw ord MAIN BLOCK 24 32Kw ord MAIN BLOCK 23 32Kw ord MAIN BLOCK 22 32Kw ord MAIN BLOCK 21 32Kw ord MAIN BLOCK 20 32Kw ord MAIN BLOCK 19 32Kw ord MAIN BLOCK 18 32Kw ord MAIN BLOCK 17 32Kw ord MAIN BLOCK16 32Kw ord MAIN BLOCK 15 32Kw ord MAIN BLOCK 14 32Kw ord MAIN BLOCK 13 32Kw ord MAIN BLOCK 12 32Kw ord MAIN BLOCK 11 32Kw ord MAIN BLOCK 10 32Kw ord MAIN BLOCK 9 32Kw ord MAIN BLOCK 8 32Kw ord MAIN BLOCK 7 32Kw ord MAIN BLOCK 6 32Kw ord MAIN BLOCK 5 32Kw ord MAIN BLOCK 4 32Kw ord MAIN BLOCK 3 32Kw ord MAIN BLOCK 2 32Kw ord MAIN BLOCK 1 32Kw ord MAIN BLOCK 0
BANK(I)
4Kword PARAMETER BLOCK 63
32Kw ord MAIN BLOCK 62 32Kw ord MAIN BLOCK 61 32Kw ord MAIN BLOCK 60 32Kw ord MAIN BLOCK 59 32Kw ord MAIN BLOCK 58 32Kw ord MAIN BLOCK 57 32Kw ord MAIN BLOCK 56 32Kw ord MAIN BLOCK 55 32Kw ord MAIN BLOCK 54 32Kw ord MAIN BLOCK 53
BANK(II) BANK(III)
32Kw ord MAIN BLOCK 52 32Kw ord MAIN BLOCK 51 32Kw ord MAIN BLOCK 50 32Kw ord MAIN BLOCK 49 32Kw ord MAIN BLOCK 48 32Kw ord MAIN BLOCK 47 32Kw ord MAIN BLOCK46 32Kw ord MAIN BLOCK 45 32Kw ord MAIN BLOCK 44 32Kw ord MAIN BLOCK 43 32Kw ord MAIN BLOCK 42 32Kw ord MAIN BLOCK 41 32Kw ord MAIN BLOCK 40 32Kw ord MAIN BLOCK 39 32Kw ord MAIN BLOCK 38 32Kw ord MAIN BLOCK 37 32Kw ord MAIN BLOCK 36
9
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Bus Operation BYTE#=VIH
Pins Mode Array Read Page Status Register Identifier Code Output Disable Program Write Stand by Deep Power Down Erase Others CE# VIL VIL VIL VIL VIL VIL VIL VIL VIH X
1)
OE# VIL VIL VIL VIL VIH VIH VIH VIH X1) X
1)
WE# VIH VIH VIH VIH VIH VIL VIL VIL X1) X
1)
RP# VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL
DQ0-15 Data Output Data Output Status Register Data Identifier Code High-Z Command/Data in Command Command High-Z High-Z
RY/BY# VOH(Hi-Z) VOH(Hi-Z) X2) VOH(Hi-Z) X2) X2) X2) X2) X2) VOH(Hi-Z)
BYTE#=VIL
Pins Mode Array Read Page Status Register Identifier Code Output Disable Program Write Stand by Deep Power Down Erase Others CE# VIL VIL VIL VIL VIL VIL VIL VIL VIH X
1)
OE# VIL VIL VIL VIL VIH VIH VIH VIH X1) X
1)
WE# VIH VIH VIH VIH VIH VIL VIL VIL X1) X
1)
RP# VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL
DQ0-7 Data Output Data Output Status Register Data Identifier Code High-Z Command/Data in Command Command High-Z High-Z
RY/BY# VOH(Hi-Z) VOH(Hi-Z) X2) VOH(Hi-Z) X2) X2) X2) X2) X2) VOH(Hi-Z)
1) 2)
X can be VIH or VIL for control pins. X at RY/BY# is VOL or VOH (Hi-Z). *The RY/BY# is an open drain output pin and indicates status of the internal WSM. When low, it indicates that WSM is Busy performing an operation. A pull-up resistor of 10K-100K Ohms is required to allow the RY/BY# signal to transition high indicating a Ready WSM condition.
10
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Software Command Definition Command List (WP# =VIH or VIL)
1st Bus Cycle Command Mode Address Read Array
Page Read
2nd Bus Cycle
1)
3rd-5th Bus Cycles (Word mode) 3rd-9th Bus Cycles (Byte mode) Mode Address Data (DQ0-15),(DQ0-7) RDi6)
Data (DQ0-15),(DQ0-7) FFH F3H
Mode
Address A20-A18 SA
2) 5) 3)
A0
Data (DQ0-15),(DQ0-7) RD0 5) ID SRD 4)
3)
Write Write Write Write Write Write Write
X X Bank Bank2) X Bank2) Bank
2) 2)
Read Read Read
Read
SA+i6)
Device Identifier
Read Status Register Clear Status Register
90H 70H 50H B0H D0H
Bank IA Bank2)
Suspend Resume
1) In the case of Word mode(BYTE#=VIH), upper byte data (DQ15-DQ8) is ignored. 2) Bank=Bank address (Bank(I)-Bank(IV): A20-18) 3) IA=ID code address: A0=VIL (Manufacturer's code): A0=VIH (Device code), ID=ID code 4) SRD=Status Register Data 5) SA=A20-A2: Page Address, A1, A0(A1-A-1):voluntary address / RD0=1st Page read data 6) SA+i: Page address(is equal to 1st Page Address of A20-A2), A1,A0(A1-A-1): voluntary address / RDi: 2nd Page read data
Command List (WP# =VIH)
1st Bus Cycle Command Mode Address Word Program Page Program Page Buffer to Flash Block Erase/Confirm Erase All Unlocked Blocks Clear Page Buffer
Single Data Load to Page Buffer
2nd Bus Cycle Mode Write Write Write Write Write Write Write Write Address WA WA0 4) WA BA6) X X WA RA7)
3) 5) 3)
3rd-129th Bus Cycles (Word mode) 3rd-257th Bus Cycles (Byte mode) Mode Address Data 1) (DQ0-15),(DQ0-7) WDn4)
Data 1) (DQ0-15),(DQ0-7) 40H 41H 0EH 20H A7H 55H
Data 1) (DQ0-15),(DQ0-7) WD WD04) D0H D0H1) D0H D0H1) WD D0H1)
3) 1) 1) 3)
Write Write Write Write Write Write Write Write
Bank Bank2) Bank Bank2) X X Bank Bank2)
2) 2)
2)
Write
WAn 4)
Flash to Page Buffer
74H F1H
1) In the case of Word mode(BYTE#=VIH),Upper byte data (DQ15-DQ8) is ignored. 2) Bank=Bank address (Bank(I)-Bank(IV): A20-A18) 3) WA=Write Address, WD=Write Data 4) WA0, WAn=Write Address, WD0, WDn=Write Data. Word mode (BYTE#=VIH) : Write address and write data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128 words (128-word x 16-bit), and also A20-A7 (block address, page address) must be valid. Byte mode (BYTE#=VIL) : Write address and write data must be provided sequentially from 00H to FFH for A6-A-1. Page size is 256 Bytes (256-byte x 8-bit), and also A20-A7 (block address, page address) must be valid. 5) WA=Write Address: A20-A7 (block address, page address) must be valid. 6) BA=Block Address : A20-A12[Bank(I)], A20-A15 [Bank(II), Bank(III), Bank(IV)] must be valid. 7) RA=Read Address: A20-A7 (block address, page address) must be valid.
11
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Software Command Definition Command List (WP# =VIL)
Software lock release operation needs following consecutive 7bus cycles.Moreover, additional 127(255) bus cycles are needed for page program operation.
Setup Command for Software Lock Release Word/Byte Program Page Program Page Buffer to Flash Block Erase/Confirm Clear Page Buffer
Single Data Load to Page Buffer
1st Bus Cycle Data Mode Address (DQ0-15/DQ0-7) Write Write Write Write Write Write Write Bank Bank Bank Bank Bank Bank Bank 60H 60H 60H 60H 60H 60H 60H
1)
2nd Bus Cycle Mode Write Write Write Write Write Write Write Address Bank Bank Bank Bank Bank Bank Bank Data1) (DQ0-15/DQ0-7) Block6) Block6) Block6) Block6) Block6) Block6) Block6)
3rd Bus Cycle Data1) Mode Address (DQ0-15/DQ0-7) Write Write Write Write Write Write Write Bank Bank Bank Bank Bank Bank Bank ACH ACH ACH ACH ACH ACH ACH
Flash to Page Buffer Setup Command for Software Lock Release Word/Byte Program Page Program Page Buffer to Flash Block Erase/Confirm Clear Page Buffer
Single Data Load to Page Buffer
4th Bus Cycle 1) Data Mode Address (DQ0-15/DQ0-7) Write Write Write Write Write Write Write Bank Bank Bank Bank Bank Bank Bank Block#6) Block#6) Block#6) Block#6) Block#6) Block#6) 6) Block#
Mode Write Write Write Write Write Write Write
5th Bus Cycle Data1) Address (DQ0-15/DQ0-7) Bank Bank Bank Bank Bank Bank Bank 7BH 7BH 7BH 7BH 7BH 7BH 7BH 8th-134th Bus Cycles(Word mode) 8th-262th Bus Cycles(Byte mode) Mode Address Data (DQ0-15/DQ0-7) WDn3)
Flash to Page Buffer
Setup Command for Program or Erase Operations Word/Byte Program Page Program Page Buffer to Flash Block Erase/Confirm Clear Page Buffer
Single Data Load to Page Buffer
6th Bus Cycle Mode Address Write Write Write Write Write Write Write Bank Bank Bank Bank X Bank Bank Data (DQ0-15/DQ0-7) 40H 41H 0EH 20H 55H 74H F1H
1)
7th Bus Cycle Mode Write Write Write Write Write Write Write Address WA2) WA03) 4) WA BA5) X WA2) RA7) Data (DQ0-15/DQ0-7) WD2) WD03) 1) D0H D0H1) D0H1) WD2) D0H1)
Write
WAn3)
Flash to Page Buffer
1) In the case of word mode(BYTE#=VIH) upper byte data (DQ15-DQ8) is ignored. 2) WA=Write Address, WD=Write Data 3) WA0, WAn=Write Address, WD0, WDn=Write Data. Write address and write data must be provided sequentially from 00H to 7FH for A6-A0(word mode) and from 00H to FFH for A6-A-1(byte mode), respectively. Page size is 128 words (128-word x 16-bit/ word mode) or Page size is 256 bytes (256-word x 8-bit/ byte mode), and also A20-A7 (block address, page address) must be valid. 4) WA=Write Address: A20-A7 (block address, page address) must be valid. 5) BA=Block Address : A20-A12[Bank(I)], A20-A15 [Bank(II), Bank(III), Bank(IV)] 6) Block=Block Address: A20-A15, Block#=A20#-A15# must be valid.
Address Block Block#
DQ7 fixed 0 fixed 0
DQ6 fixed 0 fixed 0
DQ5 A20 A20#
DQ4 A19 A19#
DQ3 A18 A18#
DQ2 A17 A17#
DQ1 A16 A16#
DQ0 A15 A15#
7) RA=Read Address: A20-A7 (block address, page address) must be valid.
12
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Block Locking
RP# VIL VIH WP# X VIL VIH Boot Locked Locked Unlocked Write Protection Provided Bank(I) Bank(II) Bank(III) Parameter/Main Main Main Locked Locked Locked Locked Unlocked Locked Unlocked Locked Unlocked
Bank(IV)
Notes Deep Power Down Mode
All Blocks Locked(Valid to operate Softw are Lock Release)
Main Locked Locked
Unlocked All Blocks Unlocked
WP# pin must not be switched during performing Read / Write operations or WSM busy (WSMS=0).
Status Register
Symbol (I/O Pin) S.R. 7 S.R. 6 S.R. 5 S.R. 4 S.R. 3 S.R. 2 S.R. 1 S.R. 0 (DQ7) (DQ6) (DQ5) (DQ4) (DQ3) (DQ2) (DQ1) (DQ0) Definition "1" Write State Machine Status Suspend Status Erase Status Program Status Block Status after Erase Reserved Reserved Reserved Ready Suspended Error Error Error "0" Bus y Operation in Progress/Completed Successful Successful Successful -
Status
13
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Device ID Code
Pins Code Manufacturer Code Device Code (Top Boot) Device Code (Bottom Boot) A0 VIL VIH VIH DQ7 "0" "0" "0" DQ6 "0" "0" "0" DQ5 "0" "1" "1" DQ4 "1" "1" "1" DQ3 "1" "1" "1" DQ2 "1" "0" "0" DQ1 "0" "0" "0" DQ0 "0" "0" "1" Hex. Data 1CH 38H 39H
In the case of word mode,The output of upper byte data (DQ15-DQ8) is "0H".
Absolute Maximum Ratings
Symbol VCC VI1 Ta Tbs Tstg Iout Parameter VCC Voltage All Input or Output Voltage1) Ambient Temperature Temperature under Bias Storage Temperature Output Short Circuit Current Conditions With Respect to GND Min. -0.2 -0.6 -40 -50 -65 Max. 4.6 4.6 85 95 125 100 Units V V C C C mA
1)Minimum DC voltage is -0.5V on input / output pins. During transitions, the level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input / output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns.
DC electrical characteristics
Symbol ILI ILO ISB2 ISB3 ISB4 ICC1 VCC Deep Power Down Current Parameter Input Leakage Current Output Leakage Current VCC Stand by Current
(Ta= -40 ~85 C and Flash VCC=3.0V~3.6V, unless otherwise noted)
Test Conditions 0V< VIN< VCC 0V< VOUT< VCC VCC= 3.6V, VIN= GND/VCC, CE#= RP#= VCC 0.3V VCC= 3.6V, VIN= VIL/VIH, RP#= VIL VCC= 3.6V, VIN= GND or VCC, RP#= GND 0.3V
Vcc = 3.6V, VIN = VIL/VIH, RP# = OE# = WE# = VIH, CE# =VIL, Iout = 0mA Vcc = 3.6V, VIN = VIL/VIH, RP# = OE# = WE# =VIH, CE# = VIL, Iout = 0mA
Min. -1.0 -10
Limits Typ.1)
Max. +1.0 +10
Units A A A A A mA mA mA mA mA mA A V V V V V V
0.1 5 0.1 20 4 5
6 25 6 30 8 10 15 35 35 200
VCC Read Current for Word / byte
5MHz 1MHz
ICC1P VCC Page Read Current ICC2 ICC3 ICC4 ICC5 VIL VIH VOL VOH1 VOH2 VLKO VCC Write Current for Word / byte VCC Program Current VCC Erase Current VCC Suspend Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Low VCC Lock Out Voltage2)
5MHz
Vcc = 3.6V, VIN = VIL/VIH, RP# = OE# = VIH, CE# = WE# = VIL
VCC = 3.6V, VIN = VIL/VIH, CE#= RP# = VIH VCC = 3.6V, VIN = VIL/VIH, CE#= RP# = VIH VCC = 3.6V, VIN = VIL/VIH, CE#= RP# = VIH -0.5 2.4 IOL = 4.0mA IOH = -2.0mA IOH = -100uA 0.85xVCC VCC-0.4 1.5
0.4 VCC+0.5 0.45
2.2
All currents are in RMS unless otherwise noted. 1) Typical values at Flash VCC=3.3V, Ta=25 C. 2) To protect against initiation of write cycle during Flash VCC power up / down, a write cycle is locked out for Flash VCC less than VLKO. If Flash VCC is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Flash VCC is less than VLKO, the alteration of memory contents may occur.
14
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC electrical characteristics Read Only Mode
(Ta=-40 ~85 C and Flash VCC=3.0V~3.6V, unless otherwise noted)
Limits Symbol tRC ta(AD) ta(CE) ta(OE) ta(PAD) tCEPH tCLZ tDF(CE) tOLZ tDF(OE) tPHZ ta(BYTE) tBHZ tOH tBCD tBAD tOEH tPS tAVAV tAVQV tELQV tGLQV Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Page Read Access Time (after 2nd access) CE# "H"Pulse width Chip Enable to Output in Low-Z Chip Enable High to Output in High-Z Output Enable to Output in Low-Z Output Enable to High to Output in High-Z RP# Low to Output High-Z BYTE# access time BYTE# low to output high-Z Output Hold from CE#, OE# and Address CE# low to BYTE# high or low Address to BYTE# high or low OE# Hold from WE# High RP# Recovery to CE# Low Min. 70
Flash VCC=3.0-3.6V
Units Max. 70 70 30 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Typ.
tELQX tEHQZ tGLQX tGHQZ tPLQZ tFL/HQV tFLQZ tOH tELFL/H tAVFL/H tWHGL tPHEL
30 0 25 0 25 150 70 25 0 5 5 10 150
-Timing measurements are made under AC waveforms for read operations.
15
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC electrical characteristics (Ta=-40 ~85 C and Flash VCC=3.0V~3.6V, unless otherwise noted) Read / Write Mode (WE# control)
Symbol tWC tAS tAH tDS tDH tOEH tCS tCH tWP tWPH tBS tBH tGHWL tBLS tBLH tDAP tDAP tDAP tDAE tWHRL tPS tAVAV tAVWH tWHAX tDVWH tWHDX tWHGL tELWL tWHEH tWLWH tWHWL tFL/HWH tWFL/H tGHWL tPHHWH tQVPH tWHRH1 tWHRH1 tWHRH1 tWHRH2 tWHRL tPHWL Parameter Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE# Hold from WE# High Chip Enable Setup Time Chip Enable Hold Time Write Pulse Width Write Pulse Width High Byte enable high or low set-up time Byte enable high or low hold time OE# Hold to WE# Low Block Lock Setup to Write Enable High Block Lock Hold from Valid SRD Duration of Auto Program Operation(Byte Mode) Duration of Auto Program Operation(Word Mode) Duration of Auto Program Operation(Page Mode) Duration of Auto Block Erase Operation Write Enable High to RY/BY# Low RP# Recovery to WE# Low Limits Flash VCC=3.0-3.6V Min. Typ. Max. 70 35 0 35 0 10 0 0 35 30 50 70 0 70 0 30 300 30 300 4 80 150 600 70 150 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ms ns ns
-Read timing parameters during command write operations mode are the same as during read only operation mode. -Typical values at Flash VCC=3.3V and Ta=25 C.
Read / Write Mode (CE# control)
Limits Symbol
tWC tAS tAH tDS tDH tOEH tWS tWH tCEP tCEPH tBS tBH tGHEL tBLS tBLH tDAP tDAP tDAP tDAE tEHRL tPS tAVAV tAVEH tEHAX tDVEH tEHDX tEHGL tWLEL tEHWH tELEH tEHEL tFL/HEH tEHFL/H tGHEL tPHHEH tQVPH tEHRH1 tEHRH1 tEHRH1 tEHRH2 tEHRL tPHEL
Parameter Min.
Write Cycle Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time OE# Hold from CE# High Write Enable Setup Time Write Enable Hold Time CE# Pulse Width CE#"H" Pulse Width Byte enable high or low set-up time Byte enable high or low hold time OE# Hold to CE# Low Block Lock Setup to Chip Enable High Block Lock Hold from Valid SRD Duration of Auto Program Operation(Byte Mode) Duration of Auto Program Operation(Word Mode) Duration of Auto Program Operation(Page Mode) Duration of Auto Block Erase Operation CE# High to RY/BY# Low RP# Recovery to CE# Low 70 35 0 35 0 10 0 0 35 30 50 70 70 70 0
Flash VCC=3.0-3.6V
Units Max.
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s ms ms ns ns
Typ.
30 30 4 150 150
300 300 80 600 70
-Timing measurements are made under AC waveforms for read operations. -Typical values at Flash VCC=3.3V and Ta=25 C.
16
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Program / Erase Time
Parameter Block Erase Time Main Block Write Time (Byte Mode) Main Block Write Time (Word Mode) Page Write Time Flash to Page Buffer Time Min. Typ. 150 2 1 4 100 Max. 600 8 4 80 150 Units ms sec sec ms s
Program Suspend / Erase Suspend Time
Parameter Program Susupend Time Erase Susupend Time Min. Typ. Max. 15 15 Unit s s
Flash VCC Power Up / Down Timing
symbol tVCS Parameter RP#=VIH Setup Time from Flash VCC min. Min. 2 Typ. Max. Unit s
During power up / down, by the noise pulses on control pins, the device has possibility of accidental erase of programming. The device must be protected against initiation of write cycle for memory contents during power up / down. The delay time of min. 2 sec is always required before read operation or write operation is initiated from the time Flash VCC reaches Flash VCC min. during power up /down. By holding RP#=VIL, the contents of memory is protected during Flash VCC power up / down. During power up, RP# must be held VIL for min. 2s from the time Flash VCC reaches Flash VCC min.. During power down, RP# must be held VIL until Flash VCC reaches GND. RP# doesn't have latch mode, therefore RP# must be held VIH during read operation or erase / program operation.
17
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Flash VCC Power up / down Timing
Read /Write Inhibit Read /Write Inhibit Read /Write Inhibit
3.3V V CC GND V IH V IL V IH V IL V IH V IL tPS tPS tVCS
RP#
CE#
WE#
AC Waveforms for Read Operation and Test Conditions
tRC
A20 -A0 (WORD) V IH A20 -A-1 (BYTE)
TEST CONDITIONS FOR AC CHARACTERISTICS Input Voltage : VIL=0V, V IH=Vcc Input Rise and Fall Times : <5ns Reference Voltage at timing measurement : (Vcc)/2 Output Load : 1 TTL gate + CL(30pF) or
1.3V 1N914
V IL
Address Valid ta(AD) tCEPH tOEH ta(OE) tOLZ
Output Valid
CE#
V IH V IL V IH V IL V IH
tDF(CE) ta(CE) tDF(OE) tOH
High-Z
OE#
WE#
V IL V OH High-Z
tCLZ
FFH
3.3kohm
DATA
VO V IH
tPS
tPHZ
DUT CL=30pF CL=30pF
RP#
V IL
- After inputting Read Array Command FFH, it is necessary to make CE# "H" pulse more than 30ns (tCEPH). And after inputting Read Array Command FFH, it is also necessary to keep 30ns to recover before starting read after WE# rises "H" in case of changing address(es) and CE#="L".
18
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC waveforms for Page Read Operation
Address A20 - A2 A1 - A0(WORD) A1 - A-1(BYTE) CE# OE# WE# DATA VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL High-Z
F3H
Page Address Valid Address Valid (Voluntary Address) 1st Address ta(OE) tCEPH 2nd ta(OE) ~ Nth
ta(AD) ta(CE)
Valid
ta(PAD)
Valid
ta(PAD)
Valid
ta(PAD)
Valid
- After inputting Page Read Command F3H, it is necessary to make CE# "H" pulse more than 30ns (tCEPH). And after inputting Page Read Command F3H, it is also necessary to keep 30ns to recover before starting read after WE# rises "H" in case of changing address(es) and CE#="L". - Once Page Read mode is valid, the mode is kept until RP# is set to VIL or the chip is powered off. - Word mode(BYTE#=VIH):N=4, Byte mode(BYTE#=VIL):N=8
Byte AC Waveforms for Read Operation
V IH V IL V IH V IL V IH V IL V IH BYTE# DATA D7-D0 DATA D14-D8 D15/A-1 V IL V OH V OL V OH V OL V IH V IL High-Z High-Z
ADDRESS A20-A0
Address Valid ta(AD)
Address Valid
CE#
tDF(CE) tBCD tBAD ta(CE) ta(OE) tOLZ tBAD ta(BYTE)
Output Valid
OE#
tDF(OE) tOH tBHZ
Valid Valid
tCLZ ta(BYTE)
Valid
ta(AD) Address Valid
D15 A-1
When BYTE# = VIH, CE# = OE# = VIL, D15/A-1 is output status. At this time, input signal must not be applied.
19
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC Waveforms for Word / Byte Program Operation (WE# Control)
ADDRESS VIH A20-A0 (Word) V IL A20-A -1(Byte) VIH CE# VIL OE# WE# DATA VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tWHRL tBLH High-Z tPS tBLS 40H tDS DIN tDH tDAP SRD FFH
Bank Address Valid
Address Valid
Bank Address Valid tAH Program
Read Status Register Write Read Array Command
tWC tCS tWP tWPH
tAS tCH
ta(CE) ta(OE) tOEH
RP# WP# BYTE# RY/BY#
tBS
tBH
AC Waveforms for Word / Byte Program Operation (CE# Control)
ADDRESS VIH A20-A0 (Word) V IL A20-A -1(Byte) VIH CE# VIL OE# WE# DATA RP# WP# BYTE# RY/BY# VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tEHRL tBLH High-Z tPS tBLS 40H tDS DIN tDH tDAP tOEH SRD FFH tWS tCEP tWH
Bank Address Valid
Address Valid
Bank Address Valid tAH Program
Read Status Register Write Read Array Command
tWC
tAS
ta(CE) ta(OE)
tBS
tBH
20
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC Waveforms for Page Program Operation (WE# Control)
ADDRESS VIH A20-A7 VIL A6-A0 (Word) VIH A6-A -1(Byte) VIL VIH CE# VIL OE# WE# DATA RP# WP# BYTE# RY/BY# VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tWHRL
The Other Bank
Bank Address Valid
The Other Bank
Bank Address Valid
Address Valid
00H 00H
Valid Valid tAH ta(CE) tOEH ta(OE) tGHWL tDH
Address Valid
01H-7EH 01H-FEH 7FH FFH
Bank Address Valid
Read Status Register Write Read Array Command
tWC tCS tWP tCH tWPH
tAS
ta(CE) ta(OE) tOEH
High-Z tPS tBLS
41H tDS
DIN
DOUT \
DIN
DIN tDAP
SRD
FFH
tBH tBS
tBLH
AC Waveforms for Page Program Operation (CE# Control)
ADDRESS VIH A20 - A7 VIL A6-A0 (Word) VIH A6-A -1(Byte) VIL CE# OE# WE# DATA RP# WP# BYTE# RY/BY# VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tEHRL tBLH tBH tBS High-Z tPS tBLS 41H DIN tDS tDAP tDH DOUT DIN DIN SRD FFH tWS tCEP tWC tWH tCEPH tOEH
Address Valid
00H 00H
Valid Valid tAH ta(CE) tGHEL ta(OE)
Address Valid
01H-7EH 01H-FEH 7FH FFH
Bank Address Valid
Read Status Register Write Read Array Command
tAS
ta(CE) ta(OE) tOEH
21
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC Waveforms for Erase Operation (WE# Control)
ADDRESS VIH A20-A0 (Word) V IL A20-A -1(Byte) VIH CE# VIL OE# WE# DATA RP# WP# BYTE# RY/BY# VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tWHRL tBS tBH High-Z tPS tBLS 20H tDS
D0H
Bank Address Valid
Address Valid
Bank Address Valid tAH Erase
Read Status Register Write Read Array command
tWC tCS tWP tWPH
tAS tCH
ta(CE) ta(OE) tOEH SRD tDH tDAE tBLH FFH
AC Waveforms for Erase Operation (CE# Control)
ADDRESS VIH A20-A0 (Word) V A20-A -1(Byte) IL VIH CE# VIL OE# WE# DATA RP# WP# BYTE# RY/BY# VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL
Bank Address Valid
Address Valid
Bank Address Valid tAH Erase
Read Status Register Write Read Array command
tWC tCEPH tWS tCEP tWH
tAS
ta(CE) ta(OE) tOEH
D0H SRD FFH
tDS High-Z tPS tBLS
20H
tDH tDAE tBLH
tBS
tBH tEHRL
22
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC Waveforms for Word / Byte Program Operation with BGO (WE# Control)
Change Bank Address Read Array in another bank Address Valid Address Valid
Program in one bank
Read Status Register
ADDRESS VIH A20 - A7 VIL A6-A0 (Word) VIH A6-A -1(Byte) VIL CE# OE# WE# DATA RY/BY# VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tCS
Bank Address Valid Address Valid
Address Valid
Address Valid
Address Valid
tWC
tAS tCH
tAH
Program tOEH ta(CE) ta(OE)
tWP
tWPH
tDS High-Z 40H DIN
tWHRL
DOUT DOUT
tDH
AC Waveforms for Word / Byte Program Operation with BGO (CE# Control)
Program in one bank
Read Status Register
Change Bank Address Read Array in another bank Address Valid Address Valid
ADDRESS VIH A20 - A7 VIL A6-A0 (Word) VIH A6-A -1(Byte) VIL CE# OE# WE# DATA RY/BY# VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tWS
Bank Address Valid Address Valid
Address Valid
Address Valid
Address Valid
tWC
tAS
tAH
Program ta(CE)
tCEP
tWH tDS tEHRL DIN tDH
tOEH
ta(OE)
High-Z
40H
DOUT
DOUT
23
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC Waveforms for Page Program Operation with BGO (WE# Control)
Program in one bank Change Bank Address Read Array in another bank Address Valid Address Valid
ADDRESS VIH A20-A7 VIL A6-A0 (Word) VIH A6-A -1(Byte) V
IL
Bank Address Valid 00H 00H
Address Valid 01H-7EH 01H-FEH 7FH FFH
Address Valid
Address Valid
CE# OE# WE# DATA RY/BY#
VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z tCS
tWC tCH tWP tWPH
tAS
tAH tOEH
ta(CE) ta(OE)
\ tDH tWHRL DIN tDS DIN
DOUT DOUT
41H
DIN
AC Waveforms for Page Program Operation with BGO (CE# Control)
Program in one bank Change Bank Address Read Array in another bank Address Valid Address Valid
ADDRESS VIH A20 - A7 VIL A6-A0 (Word) VIH A6-A -1(Byte) VIL F-CE# OE# WE# DATA F-RY/BY# VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tWS
Bank Address Valid 00H 00H
Address Valid 01H-7EH 01H - FEH 7FH FFH
tWC tWH tCEP tCEPH
tAS
tAH tOEH
ta(CE) ta(OE)
tDH High-Z 41H DIN tDS DIN
tEHRL DIN
DOUT DOUT
tDAP
24
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC Waveforms for Erase Operation with BGO (WE# Control)
ADDRESS V A20-A0 (Word) IH A20-A-1 (Byte) VIL CE# OE# WE# DATA RY/BY# VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL High-Z
20H
Program in one bank Read Status Register Change Bank Address Read Array in another bank Address Valid Address Valid
Bank Address Valid
Address Valid
tWC tCS tWP tWPH
tAS tCH tOEH
tAH ta(CE) ta(OE)
tDS
D0H
tWHRL
DOUT DOUT
tDH
AC Waveforms for Erase Operation with BGO (CE# Control)
ADDRESS VIH A20-A0 (Word) A20-A-1 (Byte) VIL VIH CE# VIL OE# WE# DATA RY/BY# VIH VIL VIH VIL VIH VIL VOH VOL High-Z
20H
Program in one bank Read Status Register Change Bank Address Read Array in another bank Address Valid Address Valid
Bank Address Valid
Address Valid
tWC
tAS tOEH
tAH ta(CE) ta(OE) tEHRL
D0H
DOUT DOUT
tWS
tCEP
tWH tDS
tDH
25
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC Waveforms for Suspend Operation (WE# Control)
ADDRESS VIH A20-A0 (Word) V A20-A-1 (Byte) IL VIH CE# VIL OE# WE# DATA VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tBLS tBLH High-Z B0H Suspend Time Bank Address Valid tAS tCS tWP tCH tOEH tAH Bank Address Valid
Read Status Register
ta(CE) ta(OE)
S.R.6,7=1
SRD
Valid
RP# WP# RY/BY#
AC Waveforms for Suspend Operation (CE# Control)
ADDRESS VIH A20-A0 (Word) A20-A-1 (Byte) VIL VIH CE# VIL OE# WE# DATA VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VOH VOL tBLS tBLH High-Z B0H tWS tCEP tWH Suspend Time Bank Address Valid tAS tAH tOEH Bank Address Valid
Read Status Register
ta(CE) ta(OE)
S.R.6,7=1
SRD
Valid
RP# WP# RY/BY#
26
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Word / Byte Program Flow Chart
Start
Page Program Flow Chart
Start
Write 40H
Write 41H
Write Address, Data
n=0
Status Register Read
Write Address n, DATA n
n+1
NO SR.7 = 1? YES Full Status Check If Desired
Write B0H? YES
NO
n = 7FH? n = FFH?
NO
YES Status Register Read
Suspend Loop
Word / Byte Program Completed
Write D0H SR.7 = 1? YES YES Full Status Check If Desired
NO
Write B0H? YES
NO
Block Erase Flow Chart
Start Page Program Completed
Suspend Loop Write D0H YES
Write 20H
Status Register Check Flow Chart
Write D0H Block Address
Start YES SR.4,5 = 1?
Status Register Read
Command Sequence Error
NO NO SR.5 = 0? NO Block Erase Error
SR.7 = 1? YES Full Status Check If Desired
Write B0H? YES
NO YES NO SR.4 = 0? YES
Program Error (Page Program)
Suspend Loop Write D0H YES SR.3 = 0? YES Pass
(Block Erase, Program)
NO
Erase Completed
Block Erase Error (Block Fail)
27
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Single Data Load to Page Buffer Flow Chart
Start
Suspend / Resume Flow Chart
Start
Write 74H
Write B0H
Suspend
Write Address, Data
Status Register Read
Load Finished?
NO S.R. 7=1? YES
NO
YES
Single Data Load To Page Buffer Completed
NO S.R. 6=1? YES Write FFH
Erase/ Program Finished
Page Buffer to Flash Flow Chart
Start
Read Array Data
Write 0EH
Read Finished?
NO
YES Write D0H
Resume
Write D0H Page Address
Operation Restart
Status Register Read
Clear Page Buffer Flow Chart
NO SR.7 = 1? YES Full Status Check If Desired
Page Buffer To Flash Completed
Write BOH? YES
NO
Start
Write 55H
Suspend Loop
Write D0H
Write D0H YES
Clear Page Buffer Completed
28
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Operation Status (WP#=VIH)
Clear Status Register 50H
Read/Standby State (Random Read Mode)
90H
Read Status Register 70H Read Device Identifier 90H FFH Read Array (Random Read) 70H
Back Bank Read State
Read Array
(Random Read)
Change Bank Address Others 3) D0H WD D0H 0EH
Page Buffer to Flash
FFH
Setup State
Clear Page Buffer Setup
55H
74H
F1H
Flash to Page Buffer
41H Page Program Setup
40H Word Program Setup
20H Block Erase Setup
A7H
Erase All Unlocked Blocks Setup
Single Data Load to Page Buffer Setup
Setup Other
Setup
D0H
Wdi I=0-127
WD
Internal State
B0H D0H B0H D0H
D0H
D0H
Others
Ready
Program & Verify Read Status Register
Erase & Verify Read Status Register
Change Bank Address Read State with BGO Read Array (Random Read) Suspend State
Read Status Register 70H
Read State with BGO Read Array (Random Read)
Change Bank Address
FFH Read Array
(Random Read)
1) In case of Page Read, F3H is used instead of FFH in Operation Status (WP#=VIH). 2) Once Page Read mode is set, Page Read mode is kept until power off or RP# is set to VIL. 3) After setting up Clear Page Buffer, D0H enables to clear Page Buffer. 4) To access any bank during Erase All Unlocked Block results Status Register Read. Although Read Status Register Command and Read Array Command can be issued under Suspend State, output data make no sense.
29
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Operation Status (WP#=VIL)
Clear Status Register 50H
Read/Standby State (Random Read Mode)
90H
Read Status Register 70H Read Device Identifier 90H FFH Read Array (Random Read) 70H
Back Bank Read State
Read Array
(Random Read)
Change Bank Address D0H Others 4) WD D0H
FFH
Others BA#
3)
Others Software Lock Release Setup
Others
Others BA
3)
Read Array
(Random Read)
Software Lock Release Setup
ACH Software Lock Release Setup
Software Lock Release Setup
60H
Change Bank Address
7BH
Software Lock Release Setup
Setup State
Clear Page Buffer Setup
55H
Single Data Load to Page Buffer Setup
74H
Flash to Page Buffer
F1H
0EH
Page Buffer to Flash
41H Page Program Setup
40H Word Program Setup
20H Block Erase Setup
Setup
Setup
Other
D0H
Wdi I=0-127
WD
Internal State
B0H D0H
D0H
Other
Ready
Program & Verify Read Status Register
B0H D0H
Erase & Verify Read Status Register
Change Bank Address
Read State with BGO
Read Array
(Random Read)
Read Status Register
Suspend State
70H
Read State with BGO
Read Array
(Random Read)
Change Bank Address
FFH Read Array
(Random Read)
1) In case of Page Read, F3H is used instead of FFH in Operation Status (WP#=VIL). 2) Once Page Read mode is set, Page Read mode is kept until power off or RP# is set to VIL. 3) BA, BA#: Block Address, Block Address# (Shown in Command List(WP#=VIL) in detail). 4) After setting up Clear Page Buffer, D0H enables to clear Page Buffer.
30
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Package Dimension
48P3R-C
31
Rev.1.0_48a_bezz
Renesas LSIs
M5M29KB/T331AVP
33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
Keep safety first in your circuit designs!
* Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
* These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. * Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. * All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). * When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. * Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. * The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. * If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. * Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. * Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
REJ03C0169 (c) 2003 Renesas Technology Corp. New publication, effective April 2003. Specifications subject to change without notice

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